Slot controller 0 FIFO arbiter
MIG
AXI4
DDR3 memory 256 MB
SPI master I2S source I2S capture
Host (USB)
GPIO (ser/des)
(Xilinx IP)
Xilinx XC7A35T FPGA ZTEX USB-FPGA 2.13a board
To backplane
Clock gen. Command handler
Control Audio
FX2 Cypress microcontroller
Interface logic
Uses external memory to create several large virtual async FIFOs
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GPIO
Slot controller 1
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Slot controller 2
Slot controller 3
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